Area-Delay Efficient Arithmetic Mixed-Radix Conversion for Fermat Moduli
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|Title:||Area-Delay Efficient Arithmetic Mixed-Radix Conversion for Fermat Moduli||Authors:||O'Donnell, Anne
Bleakley, Chris J.
|Permanent link:||http://hdl.handle.net/10197/7153||Date:||10-Jul-2011||Abstract:||Mixed Radix Conversion is an essential feature of error detection and correction in Redundant Residue Number Systems. Fermat numbers are a popular choice as moduli in these systems. However, Fermat numbers are typically implemented using Diminished–1 arithmetic which necessitates special consideration of zero in arithmetic operations. Furthermore, the sequential nature of Mixed Radix Conversion leaves it prone to considerable delay due to carry propagation in adders at each stage. In this paper, Diminished-1 arithmetic in carry save form is used to give significant reductions in area and delay compared to previously proposed hardware architectures. The percentage area reduction was found to range from 13% to 41% and that of delay from 19% to 49% for bit widths from 8 to 28 bits.||Type of material:||Journal Article||Publisher:||The Institute of Electronics, Information and Communication Engineers||Copyright (published version):||2011 IEICE||Keywords:||Fermat numbers;Mixed-radix conversion;Error detection||DOI:||10.1587/elex.8.1040||Language:||en||Status of Item:||Peer reviewed|
|Appears in Collections:||Computer Science Research Collection|
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