A 60 GHz frequency generator with implicit ÷3 divider is proposed in this work to improve the system-level efficiency and phase noise. A third-harmonic boosting technique is utilized to simultaneously generate 20GHz and sufficiently strong 60 GHz signals in order to avoid any divider operating at 60 GHz. The prototype is fabricated in 40nm CMOS and exhibits a phase noise of −100 dBc/Hz at 1MHz offset from 60 GHz carrier and 25% tuning range. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 5 dB and 4.6 dB, respectively, compared to state-of-the-art.