Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

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Title: Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs
Authors: Chen, Peng
Huang, XiongChuan
Liu, Yao-Hong
Staszewski, Robert Bogdan
et al.
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Date: 18-Sep-2015
Online since: 2015-12-14T13:22:21Z
Abstract: The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. The digital-to-time converter (DTC) is the key enabler but is nonlinearity can easily create fractional spurs. This paper analyzes the effect of the DTC nonlinearity on in-band fractional spurs and proposes a method to characterize it in a built-in fashion by means of a fine-resolution ΔΣ TDC that forms an outer loop with the DTC. The TDC is realized in 40nm CMOS and exhibits only 1.8ps rms of random jitter.
Type of material: Conference Publication
Publisher: IEEE
Start page: 283
End page: 286
Copyright (published version): 2015 IEEE
Keywords: Fractional spursTDCDTCADPLL
DOI: 10.1109/ESSCIRC.2015.7313882
Language: en
Status of Item: Peer reviewed
Is part of: Proceedings of the ESSCIRC 2015 - 41st IEEE European Solid-State Circuits Conference(ESSCIRC) 2015
Conference Details: ESSCIRC 2015 - 41st IEEE European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14-18 September 2015
Appears in Collections:Electrical and Electronic Engineering Research Collection

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