A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

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Title: A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS
Authors: Wang, Bindi
Liu, Yao-Hong
Harpe, Pieter
Staszewski, Robert Bogdan
et al.
Permanent link: http://hdl.handle.net/10197/7304
Date: 27-May-2015
Abstract: In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2015 IEEE
Keywords: Digital-to-time converter (DTC);Time-to-digital converter (TDC);ADPLL;Ultra-low power;CMOS
DOI: 10.1109/ISCAS.2015.7169140
Language: en
Status of Item: Peer reviewed
Is part of: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2015
Conference Details: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015
Appears in Collections:Electrical and Electronic Engineering Research Collection

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