A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

DC FieldValueLanguage
dc.contributor.authorWang, Bindi
dc.contributor.authorLiu, Yao-Hong
dc.contributor.authorHarpe, Pieter
dc.contributor.authorStaszewski, Robert Bogdan
dc.contributor.authoret al.
dc.date.accessioned2015-12-14T14:54:07Z
dc.date.available2015-12-14T14:54:07Z
dc.date.copyright2015 IEEEen
dc.date.issued2015-05-27
dc.identifier.urihttp://hdl.handle.net/10197/7304
dc.description2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015en
dc.description.abstractIn this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.en
dc.language.isoenen
dc.publisherIEEEen
dc.relation.ispartofProceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 2015en
dc.rights© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en
dc.subjectDigital-to-time converter (DTC)en
dc.subjectTime-to-digital converter (TDC)en
dc.subjectADPLLen
dc.subjectUltra-low poweren
dc.subjectCMOSen
dc.titleA digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOSen
dc.typeConference Publicationen
dc.internal.authorcontactotherrobert.staszewski@ucd.ie
dc.statusPeer revieweden
dc.identifier.doi10.1109/ISCAS.2015.7169140-
dc.neeo.contributorWang|Bindi|aut|-
dc.neeo.contributorLiu|Yao-Hong|aut|-
dc.neeo.contributorHarpe|Pieter|aut|-
dc.neeo.contributorStaszewski|Robert Bogdan|aut|-
dc.neeo.contributoret al.||aut|-
dc.description.othersponsorshipIMEC, Eindhoven, Netherlandsen
dc.internal.rmsid545126296
dc.date.updated2015-12-02T13:44:02Z
item.grantfulltextopen-
item.fulltextWith Fulltext-
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