Fractional spur suppression in all-digital phase-locked loops

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Title: Fractional spur suppression in all-digital phase-locked loops
Authors: Chen, Peng
Huang, XiongChuan
Staszewski, Robert Bogdan
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Date: 27-May-2015
Online since: 2016-01-07T16:43:54Z
Abstract: In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are summarized. The attention is paid to the recently proposed digital-to-time converter (DTC)-based ADPLL architecture. DTC's nonlinearity dominates the fractional spurs contribution. Its influence is modeled with a pseudo phase-domain ADPLL and its relationship with the spur level is quantitatively described. An LMS algorithm is adopted to calibrate the DTC gain. Furthermore, an improved adaptive algorithm is proposed to suppress the fractional spurs.
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2015 IEEE
Keywords: All-digital phase-locked loops (ADPLL)Complementary metal–oxide–semiconductors (CMOS)Fractional spurs
DOI: 10.1109/ISCAS.2015.7169209
Language: en
Status of Item: Peer reviewed
Is part of: Proceedings of 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015
Conference Details: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015
Appears in Collections:Electrical and Electronic Engineering Research Collection

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