Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

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Title: Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter
Authors: Tohidian, Massoud
Madadi, Iman
Staszewski, Robert Bogdan
Permanent link: http://hdl.handle.net/10197/8423
Date: 13-Oct-2014
Online since: 2017-04-06T16:17:10Z
Abstract: In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/\surd Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm2.
Funding Details: European Research Council
Type of material: Journal Article
Publisher: IEEE
Journal: IEEE Journal of Solid-State Circuits
Volume: 49
Issue: 11
Start page: 2575
End page: 2587
Copyright (published version): 2014 IEEE
Keywords: Switched capacitorCMOSDigital equalizationDiscrete timeHigh linearityHigh orderIIRLow noiseLow-pass filterLow powerPassiveReal poleReconfigurable
DOI: 10.1109/JSSC.2014.2359656
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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