A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

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Title: A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS
Authors: Wu, Wanghua
Staszewski, Robert Bogdan
Long, John R.
Permanent link: http://hdl.handle.net/10197/8627
Date: May-2014
Online since: 2017-06-26T12:31:50Z
Abstract: A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.
Type of material: Journal Article
Publisher: IEEE
Journal: IEEE Journal of Solid-State Circuits
Volume: 49
Issue: 5
Start page: 1081
End page: 1096
Copyright (published version): 2014 IEEE
Keywords: 60 GHzAll-digital phase-locked loop (ADPLL)CMOS technologyDigital calibrationFMCW radarMm-wave frequency synthesizerMulti-rate two-point frequency modulation
DOI: 10.1109/JSSC.2014.2301764
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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