A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS

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Title: A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS
Authors: Koh, Jinseok
Gomez, Gabriel
Muhammad, Khurram
Staszewski, Robert Bogdan
Haroun, Baher
Permanent link: http://hdl.handle.net/10197/8635
Date: 27-Jun-2006
Online since: 2017-07-10T14:49:55Z
Abstract: We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADC's clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5MHz.
Type of material: Journal Article
Publisher: Springer
Journal: Eurasip Journal on Wireless Communications and Networking
Volume: 2006
Start page: 1
End page: 8
Copyright (published version): 2006 the Authors
Keywords: Analog-to-digital converterBluetooth receiversCMOS
DOI: 10.1155/WCN/2006/71249
Other versions: https://jwcn-eurasipjournals.springeropen.com/articles/10.1155/WCN/2006/71249
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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