All-digital RF phase-locked loops exploiting phase prediction

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Title: All-digital RF phase-locked loops exploiting phase prediction
Authors: Zhuang, Jingcheng
Staszewski, Robert Bogdan
Permanent link: http://hdl.handle.net/10197/8637
Date: Feb-2014
Abstract: This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.
Type of material: Journal Article
Publisher: Information Processing Society of Japan
Copyright (published version): 2014 Information Processing Society of Japan
Keywords: All-digital PLL (ADPLL);Digitally controlled oscillator (DCO);Digital-to-time converter (DTC);Phase-locked loop (PLL);phase prediction;Frequency multiplication;Frequency synthesis;Frequency modulation;Time-to-digital converter (TDC);Phase modulation
DOI: 10.2197/ipsjtsldm.7.2
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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