Exponential extended flash time-to-digital converter
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|Title:||Exponential extended flash time-to-digital converter||Authors:||Chen, Peng; Staszewski, Robert Bogdan||Permanent link:||http://hdl.handle.net/10197/9038||Date:||15-Jun-2016||Online since:||2017-11-09T16:12:27Z||Abstract:||The digital-to-time converter (DTC)-based all- digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic . With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.||Funding Details:||Science Foundation Ireland||Type of material:||Conference Publication||Publisher:||IEEE||Copyright (published version):||2016 IEEE||Keywords:||DLL; TDC; Two stages; DTC-based ADPLL; Exponential||DOI:||10.1109/EBCCSP.2016.7605281||Language:||en||Status of Item:||Peer reviewed||Is part of:||Second International Conference on Event-based Control, Communication, and Signal Processing (EBCCSP)||Conference Details:||IEEE International Nordic-Mediterranean Workshop on Time-to-Digital Converters and Applications (NoMe - TDC 2016), Krakow, Poland, June, 2016|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
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