Generation of a Clocking Signal in Synchronized All-Digital PLL Networks

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Title: Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
Authors: Koskin, Eugene
Galayko, Dimitri
Feely, Orla
Blokhina, Elena
Permanent link: http://hdl.handle.net/10197/9685
Date: Jun-2018
Online since: 2019-03-26T10:26:55Z
Abstract: In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.
Type of material: Journal Article
Publisher: IEEE
Journal: IEEE Transactions on Circuits and Systems II: Express Briefs
Volume: 65
Issue: 6
Start page: 809
End page: 813
Copyright (published version): 2018 IEEE
Keywords: OscillatorsDetectorsFrequency controlClocksMathematical modelPhase frequency detectorPhase locked loopsMicroprocessor chipsNetwork topology
DOI: 10.1109/TCSII.2018.2798409
Language: en
Status of Item: Peer reviewed
Appears in Collections:Electrical and Electronic Engineering Research Collection

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