Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

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Title: Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks
Authors: Koskin, Eugene
Blokhina, Elena
Shan, Chuan
Feely, Orla
Permanent link: http://hdl.handle.net/10197/9686
Date: 29-Jun-2016
Online since: 2019-03-26T10:45:01Z
Abstract: In this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.
Funding Details: Science Foundation Ireland
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2016 IEEE
Keywords: Semiconductor device modelingLeadMeasurement uncertaintyManganeseTransient analysisSynchronization
DOI: 10.1109/NEWCAS.2016.7604784
Other versions: https://ieee-cas.org/conference/2016-14th-ieee-international-new-circuits-and-systems-conference-newcas
Language: en
Status of Item: Peer reviewed
Conference Details: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
ISBN: 9781467389006
Appears in Collections:Electrical and Electronic Engineering Research Collection

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