Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks

DC FieldValueLanguage
dc.contributor.authorKoskin, Eugene-
dc.contributor.authorBlokhina, Elena-
dc.contributor.authorShan, Chuan-
dc.contributor.authorFeely, Orla-
dc.date.accessioned2019-03-26T10:45:01Z-
dc.date.available2019-03-26T10:45:01Z-
dc.date.copyright2016 IEEEen_US
dc.date.issued2016-06-29-
dc.identifier.isbn9781467389006-
dc.identifier.urihttp://hdl.handle.net/10197/9686-
dc.description2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)en_US
dc.description.abstractIn this paper, we derive a mathematical model of an All-Digital Phase-Locked Loop (ADPLL) employing a time-to-digital phase detector. The model we suggest represents a nonlinear discrete-time map and provides significant benefits for the simulation of a single PLL, a network of PLLs or their design. In particular, the model allows us to take into account the jitter of the reference and local clocks and other noises. The mathematical model (the map) is then compared with a behavioural model implemented in MATLAB Simulink and displays identical results. The simulation of the mathematical and behavioural models are further compared with experimental measurements of a 65nm CMOS ADPLL and show a good agreement.en_US
dc.description.sponsorshipScience Foundation Irelanden_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rightsPersonal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.en_US
dc.subjectSemiconductor device modelingen_US
dc.subjectLeaden_US
dc.subjectMeasurement uncertaintyen_US
dc.subjectManganeseen_US
dc.subjectTransient analysisen_US
dc.subjectSynchronizationen_US
dc.titleDiscrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networksen_US
dc.typeConference Publicationen_US
dc.internal.authorcontactothereugene.koskin@ucd.ieen_US
dc.internal.webversionshttps://ieee-cas.org/conference/2016-14th-ieee-international-new-circuits-and-systems-conference-newcas-
dc.statusPeer revieweden_US
dc.identifier.doi10.1109/NEWCAS.2016.7604784-
dc.neeo.contributorKoskin|Eugene|aut|-
dc.neeo.contributorBlokhina|Elena|aut|-
dc.neeo.contributorShan|Chuan|aut|-
dc.neeo.contributorFeely|Orla|aut|-
dc.date.updated2019-03-22T14:34:21Z-
item.fulltextWith Fulltext-
item.grantfulltextopen-
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