Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
|Title:||Semianalytical model for high speed analysis of all-digital PLL clock-generating networks||Authors:||Koskin, Eugene
|Permanent link:||http://hdl.handle.net/10197/9824||Date:||31-May-2017||Online since:||2019-04-04T12:29:14Z||Abstract:||In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.||Funding Details:||Science Foundation Ireland||Type of material:||Conference Publication||Publisher:||IEEE||Copyright (published version):||2017 IEEE||Keywords:||Oscillators; Mathematical model; Phase locked loops; Clocks; Detectors; Frequency control; Phase frequency detector||DOI:||10.1109/ISCAS.2017.8050582||Other versions:||http://iscas2017.org/||Language:||en||Status of Item:||Peer reviewed||Conference Details:||The 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, United States of America, 28-31 May 2017||ISBN:||9781467368520|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
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