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Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition
Date Issued
2018-07-05
Date Available
2019-04-08T08:25:40Z
Abstract
In this paper we propose a new methodology to determine the delay of combinational logic circuits within the framework of statistical static timing analysis (SSTA). A new algorithm for the traversing of the timing graph is created and combined with a new technique of kernel function decomposition to find delay propagation through such a circuit. Assuming initial delays of the input signals and operation time of gates to be normally distributed, the exact analytical solution for a non-Gaussian probability density functions (PDF) of the resulting delay is obtained. Then, the approximation of a non-Gaussian PDF by a linear combination of kernel functions is proposed, and the initial Gaussian assumption is relaxed. This allowed us to build a novel closed-loop algorithm for the calculation of delay propagation in combinational circuits. Possible extensions and future steps are discussed.
Sponsorship
European Commission - European Regional Development Fund
Science Foundation Ireland
Other Sponsorship
Synopsys, Ireland
Type of Material
Conference Publication
Publisher
IEEE
Start Page
213
End Page
216
Copyright (Published Version)
2018 European Union
Language
English
Status of Item
Peer reviewed
Part of
2018 SMACD: 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
Conference Details
The 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Prague, Czech Republic, 2-5 July 2018
ISBN
978-1-5386-5152-0
This item is made available under a Creative Commons License
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