Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation

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Title: Path-Based Statistical Static Timing Analysis for Large Integrated Circuits in a Weak Correlation Approximation
Authors: Mishagli, Dmytro
Koskin, Eugene
Blokhina, Elena
Permanent link: http://hdl.handle.net/10197/9830
Date: 29-May-2019
Online since: 2019-04-08T09:09:34Z
Abstract: This work is aimed at the development of a pathbased approach to Statistical Static Timing Analysis. Timing Analysis is an absolutely essential step in the verification of Very Large Scale Integration (VLSI) designs. We propose a novel analytical methodology for the fast calculations of VLSI delay. The problem is stated in such a way that becomes equivalent to finding the maximum of a large set of correlated random variables (RVs). For this purpose, a corresponding extension of extreme value theory of weakly-correlated RVs is developed. Results of simulations showing a comparison of our approach with Monte Carlo simulations are presented. Possible applications, extensions of our methodology and future steps are discussed.
Type of material: Conference Publication
Publisher: IEEE
Copyright (published version): 2019 IEEE
Keywords: Timing graphStatistical timing alaysisVery large scare integrationExtreme value distribution
Other versions: https://www.iscas2019.org/
Language: en
Status of Item: Peer reviewed
Is part of: IEEE International Symposium on Circuits and Systems (ISCAS) 2019 in Sapporo, Japan
Conference Details: The 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 26-29 May 2019
Appears in Collections:Electrical and Electronic Engineering Research Collection

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