Analytical Approach to Statistical Logic Cell Delay Analysis and its Extension to a Timing Graph
|Title:||Analytical Approach to Statistical Logic Cell Delay Analysis and its Extension to a Timing Graph||Authors:||Mishagli, Dimitri
Brazil, Thomas J.
|Permanent link:||http://hdl.handle.net/10197/9831||Date:||16-Mar-2018||Online since:||2019-04-08T09:11:15Z||Abstract:||In this paper we propose a new methodology to determine the delay of combinational circuits within the framework of statistical static timing analysis (SSTA). The methodology is based on exact analytical solutions for the probability density functions of logic gate delays. Assuming initial delays of the input arrival times and operation time of gates to be normally distributed, the non-Gaussian distribution of the resulting delay of a gate is obtained, as well as its first two moments. This allowed us to propose a novel closed-loop algorithm for the calculation of delay propagation in combinational circuits. Possible extensions and future steps are discussed.||Funding Details:||European Commission - European Regional Development Fund
Science Foundation Ireland
|Type of material:||Conference Publication||Publisher:||ACM||Keywords:||Combinational circuits; Statistical static timing analysis; Digital integrated circuits; Gaussian distributions||Other versions:||http://www.tauworkshop.com/2018/||Language:||en||Status of Item:||Peer reviewed||Is part of:||ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2018), in Monterey, California, US||Conference Details:||The 2018 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, California, 15-16 March 2018|
|Appears in Collections:||Electrical and Electronic Engineering Research Collection|
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