Graph Partitioning for Reconfigurable Topology

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Title: Graph Partitioning for Reconfigurable Topology
Authors: Ajwani, Deepak
Ali, Shoukat
Morrison, John P.
Permanent link: http://hdl.handle.net/10197/9900
Date: 16-Aug-2012
Online since: 2019-04-11T07:46:35Z
Abstract: Optical circuit switches have recently been proposed as a low-cost, low-power and high-bandwidth alternative to electronic switches for the design of high-performance compute clusters. An added advantage of these switches is that they allow for a reconfiguration of the network topology to suit the requirements of the application. To realize the full potential of a high-performance computing system with a reconfigurable interconnect, there is a need to design algorithms for computing a topology that will allow for a high-throughput load distribution, while simultaneously partitioning the computational task graph of the application for the computed topology. In this paper, we propose a new framework that exploits such reconfigurable interconnects to achieve these interdependent goals, i.e., to iteratively co-optimize the network topology configuration, application partitioning and network flow routing to maximize throughput for a given application. We also present a novel way of computing a high-throughput initial topology based on the structural properties of the application to seed our co-optimizing framework. We show the value of our approach on synthetic graphs that emulate the key characteristics of a class of stream computing applications that require high throughput. Our experiments show that the proposed technique is fast and computes high-quality partitions of such graphs for a broad range of hardware parameters that varies the bottleneck from computation to communication.
Funding Details: Irish Research Council for Science, Engineering and Technology
Type of material: Conference Publication
Publisher: IEEE
Start page: 836
End page: 847
Copyright (published version): 2012 IEEE
Keywords: Graph-partitioning algorithmsReconfigurable topologyOptical circuit switchCo-optimization
DOI: 10.1109/IPDPS.2012.80
Language: en
Status of Item: Peer reviewed
Is part of: Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium: 21-25 May 2012 / Shanghai, China
Conference Details: The 2012 IEEE International Parallel and Distributed Symposium (IPDPS), 21-25 May 2012, Shanghai, China
ISBN: 978-1-4673-0975-2
Appears in Collections:Computer Science Research Collection

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