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  5. Geometric Algorithms for Private-Cache Chip Multiprocessors
 
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Geometric Algorithms for Private-Cache Chip Multiprocessors

Author(s)
Ajwani, Deepak  
Sitchinava, Nodari  
Zeh, Norbert  
Uri
http://hdl.handle.net/10197/9902
Date Issued
2010-09-08
Date Available
2019-04-11T08:17:59Z
Abstract
We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors.
Other Sponsorship
Natural Sciences and Engineering Research Council of Canada
Canada Research Chairs programme
MADALGO - Center for Massive Data Algorithmics, a center of the Danish National Research Foundation
Type of Material
Conference Publication
Publisher
Springer
Start Page
75
End Page
86
Series
Lecture Notes in Computer Science (LNCS. volume 6347)
Copyright (Published Version)
2010 Springer
Subjects

Shared memory

Vertical segment

Horizontal segment

Lower envelope

Intersection count

DOI
10.1007/978-3-642-15781-3_7
Language
English
Status of Item
Peer reviewed
Journal
de Berg, M., Meyer, U. (eds.). Algorithms – ESA 2010: 18th Annual European Symposium, Liverpool, UK, September 6-8, 2010. Proceedings, Part II
Conference Details
The 18th Annual European Symposium (ESA 2010), Liverpool, United Kingdom, 6-8 September 2010
ISBN
978-3-642-15780-6
ISSN
0302-9743
This item is made available under a Creative Commons License
https://creativecommons.org/licenses/by-nc-nd/3.0/ie/
File(s)
No Thumbnail Available
Name

ajwani_esa10.pdf

Size

175.18 KB

Format

Adobe PDF

Checksum (MD5)

b7110c9397e6b70454587d089e28c1a3

Owning collection
Computer Science Research Collection

Item descriptive metadata is released under a CC-0 (public domain) license: https://creativecommons.org/public-domain/cc0/.
All other content is subject to copyright.

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