McGettrick, Séamas

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McGettrick, Séamas
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McGettrick, Séamas

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  • Publication
    Rapid Functional Modelling and Simulation of Coarse Grained Reconfigurable Array Architectures
    (Elsevier, 2011-04)
    Patel, Kunjan 
    ;
    McGettrick, Séamas 
    ;
    Bleakley, Chris J. 
    Increases in the complexity of Coarse Grained Reconfigurable Array (CGRA) architectures have made implementation of new architectures difficult and time consuming. Due to the large number of design options available, it is difficult for designers to make optimal design decisions in the early stages of the design cycle. This paper proposes a novel functional modelling framework for CGRA architectures which makes the design space exploration process easier and faster. The framework allows architecture modelling, application mapping and simulation in a single environment, avoiding development of a complex tool set. The proposed approach provides flexibility which allows users to quickly investigate many design options without remodelling. The usefulness and extensibility of the framework is illustrated by presentation of a case study and associated design metrics.
      428Scopus© Citations 6
  • Publication
    SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal Processing
    (IEEE, 2011-05-03)
    Patel, Kunjan 
    ;
    McGettrick, Séamas 
    ;
    Bleakley, Chris J. 
    The promise of 24/7 patient monitoring and online diagnosis using wearable and implantable biomedical devices has engendered significant research interest in the development of low power biosignal processing platforms. Herein, a novel Coarse Grained Reconfigurable Array (CGRA) architecture is presented for low power, real time processing of biomedical signals. The proposed architecture differs from previously proposed CGRAs in that it is designed for low power, rather than for high performance. The proposed architecture was implemented in a software modeler and simulator and in Verilog. The architecture was shown to provide savings in energy consumption of up to 99% and speed up of up to 64 times compared to a conventional DSP processor for typical biosignal processing functions.
      568Scopus© Citations 11
  • Publication
    Area-Delay Efficient Arithmetic Mixed-Radix Conversion for Fermat Moduli
    (The Institute of Electronics, Information and Communication Engineers, 2011-07-10)
    O'Donnell, Anne 
    ;
    Bleakley, Chris J. 
    ;
    McGettrick, Séamas 
    Mixed Radix Conversion is an essential feature of error detection and correction in Redundant Residue Number Systems. Fermat numbers are a popular choice as moduli in these systems. However, Fermat numbers are typically implemented using Diminished–1 arithmetic which necessitates special consideration of zero in arithmetic operations. Furthermore, the sequential nature of Mixed Radix Conversion leaves it prone to considerable delay due to carry propagation in adders at each stage. In this paper, Diminished-1 arithmetic in carry save form is used to give significant reductions in area and delay compared to previously proposed hardware architectures. The percentage area reduction was found to range from 13% to 41% and that of delay from 19% to 49% for bit widths from 8 to 28 bits.
      255