Now showing 1 - 10 of 35
  • Publication
    Bifurcation Scenarios in Electrostatic Vibration Energy Harvesters
    In this paper, we present numerical bifurcation analysis of an electrostatic vibration energy harvester operating in constant-charge mode and using the in-plane gap closing transducer. We show how the system can be represented as a nonlinear oscillator and analysed using methods of nonlinear dynamics. We verify previous analytical theories and explain the behaviour of these energy harvesters, particularly in the regime between the first period doubling bifurcation and chaos.
  • Publication
    Frequency quantization in first-order digital phase-locked loops with frequency-modulated input
    Frequency granularity in a digital phase-locked loop arises from quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference signal and introduces unwanted phase jitter. Based on a nonlinear analysis of trajectories in the phase space, we have recently investigated the effect of frequency quantization in a first-order loop with a frequency-modulated input signal and have derived useful bounds on the steady-state phase jitter excursion. In this paper, we continue that work and derive the maximum modulation amplitude such that loop cycle slipping is avoided. We also examine in detail the loop behavior in acquiring phase-lock.
  • Publication
    Mode-locking in a network of kuramoto-like oscillators
    In this paper we consider a network of phase oscillators. We develop the equations that model the time evolution of the phase of each oscillator in the network. The oscillator represents a modified Kuramoto oscillator and in this study we discuss how these modifications are obtained. In the context of this study, we use this network to model a network of PLLs for distributed clock applications. We analyse analytically and numerically the synchronisation modes of this system for different types of the coupling function. We show that depending on the properties of the coupling function, the network displays either multiple coexisting synchronisation modes or only a single synchronisation mode. While in the context of clock generation, multiple synchronisation modes coexisting in the system at the same parameters are a parasitic phenomenon. However in the context of other application such as associative memory models, mode-locking can be seen a useful phenomenon. The results provide a deeper understanding of globally synchronised clock networks with applications in microprocessor design.
      303Scopus© Citations 2
  • Publication
    Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
    In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.
      311Scopus© Citations 3
  • Publication
    Limit cycles in a digitally controlled buck converter
    We describe the mathematical model of a digitally controlled buck converter. This model is an autonomous discrete-time discontinuous piecewise-linear dynamical system in three dimensions. Investigating this system, we find its equilibrium points, describe the shape and size of possible limit cycles (i.e. stable periodic motions), and derive conditions for their existence and non-existence.
      404Scopus© Citations 9
  • Publication
    Binary phase detector gain in bang-bang phase-locked loops with DCO jitter
    Bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear transfer functions in the analysis. In contrast to a linear PD, the linearized gain of a BPD depends on the rms jitter and the type of jitter (either non-accumulative or accumulative). Previous works considered the case of nonaccumulative reference clock jitter and showed that the BPD gain is inversely proportional to the rms jitter when the latter is small or large. In this brief we consider the case of accumulative DCO jitter and derive an asymptotic closed-form expression for the BPD gain which becomes exact in the limit of small and large jitter. Contrary to the reference clock jitter case, the BPD gain is constant for small DCO jitter and is inversely proportional to the square of jitter for large DCO jitter; in the latter case, the timing jitter has a normal-Laplace distribution.
      1615Scopus© Citations 14
  • Publication
    On some properties of the output of a pulsed digital oscillator working with multiple resonances
    In this paper, we study the possible output of the pulsed digital oscillator (PDO) with multiple resonant modes of the mechanical resonator in the feedback loop. PDOs are simple circuits that allow linear resonators to maintain self-sustained oscillations and can work as mass-change resonant sensors. For a resonant sensor, activation of higher vibration modes of a mechanical resonator can be a way to improve its performance. We show that the location of the sensing/actuation system affects the output and can enhance higher mechanical modes.
      246Scopus© Citations 2
  • Publication
    Linearized discrete-time model of higher order charge-pump PLLs
    In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs). The behaviour of CP-PLLs in the steady state is analysed and an important feature is developed. The nonlinear state equations of CP-PLLs are linearized around the equilibrium point. The linearized discrete-time model is finally verified using behavioral simulations in Matlab and PSpice.
      602Scopus© Citations 2
  • Publication
    Limit Cycle Behavior in a Class-AB Second-Order Square Root Domain Filter
    This paper shows how an unwanted limit cycle can be exhibited by a second-order CMOS companding filter. The filter employs the quasi-quadratic law of the MOS transistor in strong inversion and saturation to achieve compression together with a Class-AB topology to extend the dynamic range. In the zero-input case, the filter operates in the manner expected of an externally-linear circuit. However, when a standard linear IC design technique is applied to it, unwanted zero-input sustained oscillations may be observed. Simulations from PSpice and measurement results from a semi-custom realization in a 0.8μm CMOS process are used to explore this behavior. This work highlights an aspect of the behavior of such filters that must be taken into account by analog designers.
      497Scopus© Citations 2
  • Publication
    Capacitive Energy Conversion with Circuits Implementing a Rectangular Charge-Voltage Cycle Part 2: Electromechanical and Nonlinear Analysis
    In this paper, we explore and describe the electromechanical coupling which results in eKEH conditioning circuits implementing a rectangular QV cycle, including but not limited to the charge pump and Bennet’s doubler circuits. We present numerical and semi analytical analyses describing the nonlinear relationship between the oscillating mass and the conditioning circuit. We believe this is a poorly understood facet of the device and, as we will portray, effects the potential harvested energy. An approach to determine the frequency shift due to the electromechanical coupling is presented and compared with novel experimental results. We provide some examples of bifurcation behaviour and show that the only source of nonlinearity is in the coupling between the electrical and mechanical domains. This work continues from the electrical analysis presented in Part 1, providing a full insight into the complex behaviour of the electromechanical coupling.
      392Scopus© Citations 19