Now showing 1 - 10 of 35
  • Publication
    Dielectric charge control in electrostatic MEMS positioners / varactors
    A new dynamical closed-loop method is proposed to control dielectric charging in capacitive MEMS positioners/ varactors for enhanced reliability and robustness. Instead of adjusting the magnitude of the control voltage to compensate the drift caused by the dielectric charge, the method uses a feedback loop to maintain it at a desired level: the device capacitance is periodically sampled and bipolar pulses of constant magnitude are applied. Specific models describing the dynamics of charge and a control map are introduced. Validation of the proposed method is accomplished both through discrete-time simulations and with experiments using MEMS devices that suffer from dielectric charging.
      712Scopus© Citations 23
  • Publication
    Frequency quantization in first-order digital phase-locked loops with frequency-modulated input
    Frequency granularity in a digital phase-locked loop arises from quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference signal and introduces unwanted phase jitter. Based on a nonlinear analysis of trajectories in the phase space, we have recently investigated the effect of frequency quantization in a first-order loop with a frequency-modulated input signal and have derived useful bounds on the steady-state phase jitter excursion. In this paper, we continue that work and derive the maximum modulation amplitude such that loop cycle slipping is avoided. We also examine in detail the loop behavior in acquiring phase-lock.
      223
  • Publication
    Statistical analysis of first-order bang-bang phase-locked loops using sign-dependent random-walk theory
    Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear due to the hard nonlinearity introduced by the binary phase detector (BPD). This paper provides an exact statistical analysis of the steady-state timing jitter in a first order BBPLL when the reference clock is subject to accumulative jitter. By elaborating on the analogy of viewing a first-order BBPLL as a single-integration delta modulator (DM) in the phase domain, we are able to relate hunting jitter and slew-rate limiting in a BBPLL to granular noise and slope overload in a DM. The stochastic timing-jitter behavior is modeled as a sign-dependent random walk, for which we obtain the asymptotic characteristic function and analytical expressions for the first four cumulants. These expressions are applied to the BBPLL to statistically analyze the static timing offset and the RMS timing jitter, including the effect of a frequency offset. The analysis shows that the RMS timing jitter is constant for small RMS clock jitter and grows quadratically with large RMS clock jitter, and that there exists an optimal bang-bang phase step for minimum RMS timing jitter. Computing the kurtosis reveals the effect of the BPD nonlinearity: the timing jitter is largely non-Gaussian.
      649Scopus© Citations 18
  • Publication
    Semianalytical model for high speed analysis of all-digital PLL clock-generating networks
    In this paper, we propose the model of a network consisting of All-Digital Phase-Locked Loop Network in application to Clock-Generating Systems. The method is based on a solution of a system of non-linear finite-difference stochastic equations and allows us to perform high speed simulations of a distributed Clock Network on arbitrary topology. The result of our analysis show a good agreement with experimental measurements of a 65nm CMOS All-Digital Phase-Locked Loop Network.
      430Scopus© Citations 3
  • Publication
    Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
    In this brief, we propose a discrete-time framework for the modeling and studying of all-digital phase-locked loop (ADPLL) networks with applications in clock-generating systems. The framework is based on a set of nonlinear stochastic iterating maps and allows us to study a distributed ADPLL network of arbitrary topology. We determine the optimal set of control parameters for the reliable synchronous clocking regime, taking into account the intrinsic noise from both local and reference oscillators. The simulation results demonstrate very good agreement with experimental measurements of a 65-nm CMOS ADPLL network. This brief shows that an ADPLL network can be synchronized both in frequency and phase. We show that for a large Cartesian network the average network jitter increases insignificantly with the size of the system.
      442Scopus© Citations 10
  • Publication
    Bifurcation Scenarios in Electrostatic Vibration Energy Harvesters
    In this paper, we present numerical bifurcation analysis of an electrostatic vibration energy harvester operating in constant-charge mode and using the in-plane gap closing transducer. We show how the system can be represented as a nonlinear oscillator and analysed using methods of nonlinear dynamics. We verify previous analytical theories and explain the behaviour of these energy harvesters, particularly in the regime between the first period doubling bifurcation and chaos.
      311
  • Publication
    Phase jitter dynamics of first-order digital phase-locked loops with frequency-modulated input
    Inherent to digital phase-locked loops is frequency quantization in the number-controlled oscillator which prevents the loop from locking exactly onto its reference signal and introduces unwanted phase jitter. This paper investigates the effect of frequency quantization in a first-order loop with a frequency-modulated input signal. Using tools of nonlinear dynamics, we show that, depending on the modulation amplitude, trajectories in the phase space eventually fall into either an invariant region or a trapping region, the boundaries of which give useful bounds on the steady-state phase jitter excursion. We also derive a sufficient condition for the maximum modulation amplitude to prevent loop cycle slipping.
      370Scopus© Citations 2
  • Publication
    Combined mechanical and circuit nonlinearities in electrostatic vibration energy harvesters
    The aim of this paper is to study an electrostatic vibration energy harvester that utilises a nonlinear resonator. A vibration energy harvester represents a system where a mechanical resonator driven by ambient vibrations is coupled with a conditioning electronic circuit, which acts as a damper and converts mechanical energy into electrical. If a nonlinear resonator is embedded into the conditioning circuit, nonlinearity will appear from both mechanical and circuit components of the system. We expand the analytical approach that we developed in our previous works to the case of combined mechanical and circuit nonlinearities. This allow us to analyze steady-state behavior and compare it with the linear case. In addition, we discuss a specific nonlinear phenomena that is introduced by the discontinuity of the system — the sliding bifurcation. We show that the onset of steady-state quasi-harmonic oscillations occur through the disappearance of sliding motion.
      430Scopus© Citations 7
  • Publication
    Analysis of Limit Cycles in a PI Digitally Controlled Buck Converter
    Digital control of power converters has been an area of considerable research interest in recent times. One of the problems which arises in these systems is that of the limit cycle oscillations that occur due to quantization in the feedback loop. This paper investigates the limit cycle oscillations that occur in the digitally controlled version of the buck converter with a proportional-integral controller. The amplitude and frequency of the oscillations that may occur on two duty cycle levels are investigated and related to the controller gain parameters. The analysis shows that it is not possible to guarantee that limit cycle oscillations on two levels will not occur simply by adjusting the gain parameters, and yields a condition which will prevent oscillations on two levels from occurring.
      1078Scopus© Citations 10
  • Publication
    Control of MEMS vibration modes with Pulsed Digital Oscillators : Part I — theory
    The aim of this paper is to show that it is possible to excite selectively different mechanical resonant modes of a MEMS structure using Pulsed Digital Oscillators (PDOs). This can be done by simply changing the working parameters of the oscillator, namely its sampling frequency or its feedback filter. A set of iterative maps is formulated to describe the evolution of the spatial modes between two sampling events in PDOs. With this lumped model, it is established that under some circumstances PDO bitstreams related to only one of the resonances can be obtained, and that in the antioscillation regions of the PDO the mechanical energy is absorbed into the electrical domain on average. The possibility of selecting for a given resonant frequency the oscillation and antioscillation behaviour allows one to obtain oscillations at any given resonant mode of the MEMS structure.
      373Scopus© Citations 15