Now showing 1 - 2 of 2
  • Publication
    Efficient Concurrent Error Detection and Correction of Soft Errors in NTT-based Convolutions
    (The Institution of Engineering and Technology, 2009-06) ; ; ;
    A system for soft error detection and correction is proposed for digital Integrated Circuit (IC) implementation of convolution. The convolution is implemented in a Residue NumberSystem using Fermat Number Theoretic Transforms. The flexibility afforded by the Modified Overlap Technique in allowing transforms of differing lengths in a convolution makes it possible to easily detect and correct soft errors by means of a Single Redundant Channel and pattern matching technique. The proposed system gives area reductions in the majority of cases examined, when compared with Triple Modular Redundancy. In the case of large (e.g. 28 and 32 bit) word lengths, the proposed system provides area reductions of up to 30%.
  • Publication
    Area-Delay Efficient Arithmetic Mixed-Radix Conversion for Fermat Moduli
    (The Institute of Electronics, Information and Communication Engineers, 2011-07-10) ; ;
    Mixed Radix Conversion is an essential feature of error detection and correction in Redundant Residue Number Systems. Fermat numbers are a popular choice as moduli in these systems. However, Fermat numbers are typically implemented using Diminished–1 arithmetic which necessitates special consideration of zero in arithmetic operations. Furthermore, the sequential nature of Mixed Radix Conversion leaves it prone to considerable delay due to carry propagation in adders at each stage. In this paper, Diminished-1 arithmetic in carry save form is used to give significant reductions in area and delay compared to previously proposed hardware architectures. The percentage area reduction was found to range from 13% to 41% and that of delay from 19% to 49% for bit widths from 8 to 28 bits.