Now showing 1 - 5 of 5
  • Publication
    Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs
    The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. The digital-to-time converter (DTC) is the key enabler but is nonlinearity can easily create fractional spurs. This paper analyzes the effect of the DTC nonlinearity on in-band fractional spurs and proposes a method to characterize it in a built-in fashion by means of a fine-resolution ΔΣ TDC that forms an outer loop with the DTC. The TDC is realized in 40nm CMOS and exhibits only 1.8ps rms of random jitter.
      462Scopus© Citations 9
  • Publication
    Time domain converters and ultra-low-power all-digital phase-locked-loop
    Internet-of-Things promise the devices the ability to connect, collect and exchange data with little or no human-to-human or human-to-computer intervention. The continued demand for low cost and low power of wireless communications drive research that explores new architectures and techniques in the RF front-end. Time-domain operations are favored by the technology scaling, thanks to the steeper and steeper transition edges having the ability to carry information. Two fundamental time-domain data converters are time-to-digital converter (TDC) and digital-to-time converter (DTC). First, a novel discharging constant-slope DTC is proposed, consuming merely 31 μW running at 40 MHz. Taking advantage of the constant-slope operation, it achieves 1.07 LSB in a 9-bit implementation with a typical resolution of 148 fs. This work also uncovers for the first time two effects that are compensating each other: channel length modulation is compensated by the ramp node varactor. Compared with other constant-slope DTC counterparts and other DTC architectures, the proposed work achieves an outstanding performance. Then, the other basic time-domain block, time-to-digital converter, is introduced thoroughly in the introduction chapter with popular TDC architectures investigated and summarized. The proposed TDC work targets built-in-self-test applications. With the help of the proposed system self-calibration method, the non-ideal effects of analog blocks can be calibrated in a digital manner. The system achieves pico-second level precision with a low-quality clock available in the SoC environment. Two all-digital phase-locked-loops are designed with different applications and techniques. The first one utilizes a ΣΔ technique to dither the DTC control codes to suppress fractional spurs. In the mm-wave applications, it achieves around -30 dBc fractional spur at 60 GHz output. With the help of low noise contribution from the DTC and narrow TDC range benefited from Vernier architecture, the PLL achieves 213{277 fs RMS jitter in 57.5{67.2 GHz tuning range while consuming only 40mW. The second one is applied in the Bluetooth low energy applications. It pursues low power consumption for the PLL so that the battery life can be extended for the radios. With the help of the improved constant-slope DTC and hybrid TDC, together with an optimized low power inverse-class- F VCO, the PLL achieves sub-half-mW power consumption with 1 ps RMS jitter.
  • Publication
    A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
    This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.
      594Scopus© Citations 12
  • Publication
    Fractional spur suppression in all-digital phase-locked loops
    In this paper, fractional spur suppression techniques for all-digital PLLs (ADPLLs) are summarized. The attention is paid to the recently proposed digital-to-time converter (DTC)-based ADPLL architecture. DTC's nonlinearity dominates the fractional spurs contribution. Its influence is modeled with a pseudo phase-domain ADPLL and its relationship with the spur level is quantitatively described. An LMS algorithm is adopted to calibrate the DTC gain. Furthermore, an improved adaptive algorithm is proposed to suppress the fractional spurs.
      1015Scopus© Citations 1
  • Publication
    Exponential extended flash time-to-digital converter
    The digital-to-time converter (DTC)-based all- digital phase locked loop (ADPLL) attracts more and more attention due to its ultra-lower power consumption characteristic [1]. With DTC, the time-to-digital converter's (TDC) requirements are relaxed, not only for its range but also for its nonlinearity. However, the shortened TDC range, which is less than one digital controlled oscillator (DCO) output period in the new architecture makes the settling time longer and the TDC gain calibration difficult. This work introduces a technique to extend the TDC range by 16 times to accelerate the settling process, while the extended part can be disabled when ADPLL is in lock. Furthermore, the TDC gain calibration is easier.