Now showing 1 - 3 of 3
  • Publication
    Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection
    Digital transmitter (DTX) offers the desired signal efficiency and flexibility than its analog counterpart by merging signal amplification and modulation. Yet, the high-speed digital baseband interface is challenging and bulky for achieving low out-of-band noise. This Brief is an analytical study of the DTX linear interpolation technique, which can be adapted easily for optimizing the replica rejection and noise-filtering capabilities of the DTX.
      513Scopus© Citations 4
  • Publication
    A Vertically Integrated RFDAC with Analog Linear Interpolation in 28-nm CMOS
    (University College Dublin. School of Electrical and Electronic Engineering, 2021)
    Wireless systems in high data-rate applications, such as cell phones, laptops as well as small base stations, are increasingly required to support wide signal bandwidth and complex modulation schemes. At the same time, they are pushed towards higher levels of system integration and smaller silicon die area for the sake of cost. The demands of transmitting wideband signals have created plenty of challenges to the digital signal processor (DSP) in the transmitter. In DSP, the baseband signals are generated and up-sampled to higher bandwidths and sampling rates. The digital filter used in the up-sampling process should have a certain order and speed determined by the system specifications. As wideband baseband signals become popular in emerging applications, high-order and high-speed digital filters are required, increasing the complexity and power consumption of DSP. It motivates us to consider whether the complex digital processing can be partially done by on the other, i.e., or non-DSP side or “radio frequency” side, as the high frequency carrier already exists in the RF domain and it can be potentially used for baseband signal processing. As one of the key blocks in a communication system, the conventional transmitter comprises a considerable mount of analog circuits, such as the digital-to-analog converter, the low-pass filter, and the RF modulator. Firstly, these analog blocks are sensitive to the environment. Therefore, careful attention is required during the layout. Secondly, it is usually unavoidable to redesign these analog blocks when the system specifications are modified. These features constrain the transmitter to fully take advantage of the advanced CMOS technology. Alternatively, the radio-frequency digital-to-analog converter (RFDAC) which contains the all-digital modulator and digitally controlled power amplifier (PA) can fully take advantage of the technology scaling and robustness of the digital circuits. In this thesis, a vertically integrated RFDAC is proposed and implemented. As the RFDAC naturally features the digitally intensive architecture, it demonstrates better reconfigurability, amenability to technology porting, and capability of extensive self-calibration and self-testing. All these features match well with today’s demands for communication systems that are highly integrated, consume little space, and are power efficient. The PA is the key power-hungry building block of the transmitter. Thus, any improvement on its efficiency can significantly benefit the application. Furthermore, to efficiently deliver power to the load, the PA needs at least one matching network, which is composed of transformers, inductors and capacitors. These passive devices occupy large areas on the chip, making the PA the most area hungry and, consequently, the most expensive block of the entire transmitter. This naturally leads to research on how to enhance the PA’s efficiency with smaller area. To align with the all-digital modulator in RFDAC, digitally controlled switch-mode power amplifiers of class-D/E/F are proposed and implemented. To reduce the PA area, a vertical integration approach is proposed, first time ever in an RFDAC. The vertical integration takes advantage of the fact that area-consuming passive components of the matching network, like inductors and transformer, are fabricated in top metal layers. The active blocks can be built with lower metal layers and put underneath of the passive components. As a result, the passive components, which are on-chip yet occupy a significant portion of the area, will not require their dedicated silicon areas, thus leading to a lower silicon manufacturing cost. By far, the vertical integration method has been tried in designs of limited output power, due to the reason that the metal utilization needs to be carefully organized for passive devices including shielding, active circuits, power supply and ground. It is even more challenging for high output power systems, owing to fact that the top metal layers cannot be used for power supply or ground any longer to retain low impedance. This issue should be solved in the scenario of designing a high output power RFDAC by adopting the proposed vertical integration. As the crowning of this research, a wideband 2.4 GHz 2×9-bit Cartesian RFDAC has been successfully demonstrated in TSMC 28-nm LP CMOS. An 8× analog linear interpolation at the RF rate is proposed to suppress replicas close to the carrier while avoiding any high-order and high-speed digital filters in the digital processing back-end. The multiport transformer is adopted in the matching network to improve the back-off efficiency. The RFDAC operates across the 3-dB bandwidth from 1.8 to 2.8 GHz. The measured peak output power and drain efficiency at the center frequency of 2.4 GHz are 17.47 dBm and 17.6% respectively, while the peak efficiency is 19.03%. Moreover, the 6-dB back-off efficiency is at 66% of the measured peak efficiency. Vertical integration is introduced in the physical implementation, where all key active circuitry is located underneath the transformer-based matching network, achieving a core area of merely 0.35 mm2. According to some rough estimates, the core area has been reduced to 60% of the area achieved by adopting the transitional integration method. The vertical integration enables this implemented RFDAC achieving a much smaller area among comparable prior arts.
      696
  • Publication
    A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
    This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.
      780Scopus© Citations 14