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    Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition
    In this paper we propose a new methodology to determine the delay of combinational logic circuits within the framework of statistical static timing analysis (SSTA). A new algorithm for the traversing of the timing graph is created and combined with a new technique of kernel function decomposition to find delay propagation through such a circuit. Assuming initial delays of the input signals and operation time of gates to be normally distributed, the exact analytical solution for a non-Gaussian probability density functions (PDF) of the resulting delay is obtained. Then, the approximation of a non-Gaussian PDF by a linear combination of kernel functions is proposed, and the initial Gaussian assumption is relaxed. This allowed us to build a novel closed-loop algorithm for the calculation of delay propagation in combinational circuits. Possible extensions and future steps are discussed.
    Scopus© Citations 6  387