De La Cruz Blas, Carlos A.Carlos A.De La Cruz BlasFeely, OrlaOrlaFeely2012-08-102012-08-102011 Sprin2011-08Analog Integrated Circuits and Signal Processing0925-1030http://hdl.handle.net/10197/3741This paper shows how an unwanted limit cycle can be exhibited by a second-order CMOS companding filter. The filter employs the quasi-quadratic law of the MOS transistor in strong inversion and saturation to achieve compression together with a Class-AB topology to extend the dynamic range. In the zero-input case, the filter operates in the manner expected of an externally-linear circuit. However, when a standard linear IC design technique is applied to it, unwanted zero-input sustained oscillations may be observed. Simulations from PSpice and measurement results from a semi-custom realization in a 0.8μm CMOS process are used to explore this behavior. This work highlights an aspect of the behavior of such filters that must be taken into account by analog designers.387845 bytesapplication/pdfenThe final publication is available at www.springerlink.comSquare root domainLog domainFiltersLog domain filtersLimit cyclesJournal Article68217118110.1007/s10470-011-9599-4https://creativecommons.org/licenses/by-nc-sa/1.0/