Wang, BindiBindiWangLiu, Yao-HongYao-HongLiuHarpe, PieterPieterHarpeStaszewski, Robert BogdanRobert BogdanStaszewskiet al.2015-12-142015-12-142015 IEEE2015-05-27http://hdl.handle.net/10197/73042015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24 - 27 May 2015In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.en© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Digital-to-time converter (DTC)Time-to-digital converter (TDC)ADPLLUltra-low powerCMOSConference Publication10.1109/ISCAS.2015.71691402015-12-02https://creativecommons.org/licenses/by-nc-nd/3.0/ie/