Shahmohammadi, MinaMinaShahmohammadiBabaie, MasoudMasoudBabaieStaszewski, Robert BogdanRobert BogdanStaszewski2017-04-182017-04-182016 IEEE2016-11IEEE Journal of Solid-State Circuitshttp://hdl.handle.net/10197/8433In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function of a nonzero dc value, which facilitates the 1/f noise upconversion into the oscillator's 1/f3 phase noise. We demonstrate that if the ω0 tank exhibits an auxiliary resonance at 2ω0, thereby forcing this current harmonic to flow into the equivalent resistance of the 2ω0 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor-and transformer-based tanks by exploiting different behaviors of inductors and transformers in differential-and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40 nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.en© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Class-D oscillatorClass-F oscillatorDigitally controlled oscillatorFlicker noiseFlicker noise upconversionImpulse sensitivity function (ISF)Phase noise (PN)Voltage-biasedRF oscillatorA 1/f noise up-conversion reduction technique for voltage-biased RF CMOS oscillatorsJournal Article51112610262410.1109/JSSC.2016.26022142017-03-17https://creativecommons.org/licenses/by-nc-nd/3.0/ie/