Zong, ZhiruiZhiruiZongBabaie, MasoudMasoudBabaieStaszewski, Robert BogdanRobert BogdanStaszewski2015-12-102015-12-102015 IEEE2015-05-19http://hdl.handle.net/10197/72852015 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, Arizona, USA, 17 - 19 May 2015A 60 GHz frequency generator with implicit ÷3 divider is proposed in this work to improve the system-level efficiency and phase noise. A third-harmonic boosting technique is utilized to simultaneously generate 20GHz and sufficiently strong 60 GHz signals in order to avoid any divider operating at 60 GHz. The prototype is fabricated in 40nm CMOS and exhibits a phase noise of −100 dBc/Hz at 1MHz offset from 60 GHz carrier and 25% tuning range. The phase noise and FoMT (figure-of-merit with tuning range) are improved by 5 dB and 4.6 dB, respectively, compared to state-of-the-art.en© © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.60 GHzOscillatorMm-waveHarmonic boostHarmonic extractionDividerConference Publication27928210.1109/RFIC.2015.73377592015-12-02https://creativecommons.org/licenses/by-nc-nd/3.0/ie/