Li, YueYueLiWang, XiaoyuXiaoyuWangZhu, AndingAndingZhu2020-04-302020-04-302019 IEEE2020-03IEEE Transactions on Microwave Theory and Techniques0018-9480http://hdl.handle.net/10197/11359In this article, we present a novel technique to build digital predistorters that can linearize broadband power amplifiers (PAs) using reduced sampling rates. In contrast to conventional digital predistortion (DPD) where oversampling is necessary to avoid aliasing effect, the proposed method cancels the aliasing distortion using a sliced multistage cancellation scheme. A large reduction of sampling rate can be achieved in digital implementation of DPD, significantly reducing power consumption and implementation cost. Experimental results show that a DPD with a sampling rate of merely 1.5x, instead of 5x, signal bandwidth, can still produce satisfactory performance within the linearization bandwidth but consume only one-third of power, compared with that using the conventional approaches. The proposed technique provides a promising solution for the next-generation 5G systems, where large signal bandwidths are required.en© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.BandwidthNonlinear distortionPower demandPredistortionBroadband communicationClocksJournal Article6831054106410.1109/tmtt.2019.29448132019-10-3113/RC/207716/IA/444917/NSFC/4850https://creativecommons.org/licenses/by-nc-nd/3.0/ie/