Now showing 1 - 10 of 53
  • Publication
    A High IIP2 SAW-Less Superhetero-dyne Receiver with Multi-Stage Harmonic Rejection
    In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1-2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8-14 dBm, while drawing only 22-40 mW in various operating modes.
      442Scopus© Citations 31
  • Publication
    A 30-GHz Class-F23 Oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz l/f3 Corner
    This paper presents a mmW frequency generation stage aimed at minimizing phase noise via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A second-harmonic tank resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for shortest and well controlled common-mode current return path. Class-F operation with third-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10 GHz tank at the 30 GHz frequency generation while providing implicit divide-by-3 functionality. The proposed 27.3-31.2 GHz oscillator is implemented in 28-nm CMOS. It achieves phase noise of-106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dB at 27.3GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.
      316Scopus© Citations 10
  • Publication
    Cryogenic Low-Drop-Out Regulators Fully Integrated with Quantum Dot Array in 22-nm FD-SOI CMOS
    This brief presents two monolithically integrated output-capacitor-less ("caples") low-drop-out (LDO) linear regulators implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) to support on-die scalable CMOS charge-based quantum processing unit (QPU). The proposed LDOs are used to regulate 0.8 V and 1.5 V input voltages for the programmable capacitive digital-to-analog converter (CDAC) and single-electron detector, respectively. Measured results show that both LDOs can maintain their respective output voltages with a maximum deviation <2% from ~270 K down to ~ 3.7 K.
      89Scopus© Citations 1
  • Publication
    A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path
    (Institute of Electrical and Electronics Engineers (IEEE), 2018-04-24) ; ;
    This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of -106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of -184 dBc/Hz at 27.3 GHz. Its flicker phase-noise (1/f3) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.
      378Scopus© Citations 76
  • Publication
    A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS
    A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 μs. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz rms for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Ω load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.
      750Scopus© Citations 144
  • Publication
    An CMOS impedance sensor for MEMS adaptive antenna matching
    This paper proposes a new calibration mechanism for passive adaptive cellular antenna matching network containing MEMS-based tunable devices. To avoid expensive and bulky couplers and reference circuitry, the tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates 2-bit update controls for the tuning algorithm, which drives the MEMS-based tunable devices. The impedance sensing IC is designed to operate in the frequency range of 1.7–2.7 GHz and the clock frequency is 50 kHz.
  • Publication
    Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation
    In this paper, we present a design technique for broadband linearized fully integrated GaN power amplifiers (PAs). The minimum inductor bandpass filter structure is used as the output matching network to achieve low loss and high out-of-band attenuation. Two parallel transistors with unbalanced gate biases are used to mitigate nonlinearity of their transconductance and input capacitance, and consequently, compensate AM-PM distortion of the PA. A fully integrated GaN PA prototype provides 35.1–38.9 dBm output power and 40-55% power-added efficiency (PAE) in 2.0–4.0 GHz. For a 64-QAM signal with 8-dB peak-to-average power ratio (PAPR) and 100-MHz bandwidth at 2.4 GHz, average output power of 32.7 dBm and average PAE of 31% are measured with −30.2 dB error vector magnitude (EVM).
  • Publication
    A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters
    We present a broadband dual-channel power amplifier (PA) with crosstalk suppression for multi-input multi-output (MIMO) communications. Operation of MIMO system with crosstalk is theoretically evaluated for two popular coding schemes including the space-time coding and linear precoding. Design challenges of a multi-channel PA on a single chip are investigated and circuit techniques, including second-harmonic trapping integrated into the output matching network and the use of back-via lines to isolate the channels, are proposed to mitigate the inter-channel crosstalk. A fully integrated dual-channel PA prototype, implemented using a 250-nm GaN-on-SiC process, provides 34.9–36.3 dBm output power, 44–49% power-added efficiency (PAE), 11.3–12.3 dB power gain, 31.0–34.2 dB second-harmonic rejection, and –28.1 dB to –25.7 dB inter-channel crosstalk across 4.5–6.5 GHz. For a 100-MHz 256-QAM signal with 7.2 dB peak-to-average power ratio (PAPR), the PA achieves 29.9 dBm average output power, 30% average PAE–, 38.2/–39.1 dBc adjacent channel leakage ratio (ACLR), and –28.2 dB (3.9%) rms error vector magnitude (EVM), without using digital predistortion (DPD). Effect of crosstalk on linearity of the dual-channel PA is also measured and it is shown that for a 256-QAM signal EVM can increase by 3–8 dB, depending on relative power levels of the two channels.
      211Scopus© Citations 11
  • Publication
    A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS
    This paper proposes a power-efficient capacitor-array-based digital-to-time converter (DTC) using a constant-slope approach. Fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate starting supply voltage of the constant slope fed to a fixed threshold comparator. The proposed DTC consumes only 15 μW from a 1V supply, while achieving fine resolution of 103 fs when running at 40 MHz. The measured INL and DNL are 0.73/0.35 LSB within a 5-bit range. The DTC achieves the best figure-of-merit of 8.5 fJ among state-of-the-art when normalizing the product of power and INL to the product of input frequency and range.
      596Scopus© Citations 12
  • Publication
    A waveform-shaping millimeter-wave oscillator with 184.7dBc/Hz FOM in 40nm digital CMOS process
    In this paper, a topology for millimeter-wave (mm­ wave) oscillator with a waveform-shaping operation is proposed with improved phase-noise. The 3rd harmonic enhancement for enforcing a pseudo-square voltage waveform and adjustable tuning-banks for wide tuning range are simultaneously achieved, based on a multi-stage broadside-coupled transformer (MSBCT) with recon gurable coupling factors at mm-wave. Meanwhile, to meet the high-Q, high-resolution, and metal density limits, a novel 3D self-shielded capacitor is developed for implementation of tuning-banks operating at mm-wave. To verify the mechanism of the structures above, a waveform-shaping mm-wave digitally­ controlled oscillator (DCO) is fabricated. The proposed oscillator has a state-of-the-art gure-of-merit (FoM) of 184.7dBcIHz at 58.1 GHz under 110°C, despite being realized in a digital CMOS 40nm process without customary ultra-thick metal option. The resolution for this DCO is about 2.5MHz within the whole tuning range. The chip core size is 315um by llOum.Index Terms-3D self-shielded capacitor, digitally-controlled oscillator (DCO), multi-stage broadside-coupled transformer (MSBCT), waveform-shaping, millimeter-wave (mm-wave).
      219Scopus© Citations 6