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  • Publication
    Fully Integrated Switched-Capacitor DC-DC Converter in All-Digital PLL for IoT Applications
    (University College Dublin. School of Electrical and Electronic Engineering, 2019-11-19)
    The development of Internet of Things (IoT) is driving research and innovation to connect our day-to-day ‘things’, such as wearable devices, wireless electronics, implantable sensors, and smart appliances. The ‘smart’ nodes in IoT applications generally comprise wireless communication blocks, power management units (PMUs), energy sources, digital signal processing, and sensors, and are often implemented as system-on-chip (SoC) solutions. Consequently, high power efficiency, low power consumption, small silicon area, and low cost are the main requirements for IoT SoC implementation. Several popular standards, such as Bluetooth low energy (BLE), are defined for IoT. The development of radios for IoT node devices has spurred research in ultra-low-power (ULP) all-digital phase-locked loops (ADPLLs) performing as local oscillators (LOs). The IoT concept entails stringent conditions on the size and weight of the battery. In spite of recent advancements, the IoT system lifetime is still limited by the power consumption of its radio, and in particular the LO. Consequently, this triggers inconvenient battery replacements, which limits their marketing attractiveness. The lifetime could be easily extended with larger batteries but that comes at a price of increased weight and size and it is clearly against the vision of IoT miniaturization. Energy harvesters can significantly extend the IoT lifetime up to the point of perpetual operation. Among them, solar cells have gained a significant popularity due to their high-power density and low cost. However, they typically provide low voltages, especially when operating indoors, often well below the typical supply of CMOS circuits. This is likely to degrade performance of important ADPLL building blocks. An inverter-based time-to-digital converter (TDC) is such an example. In this dissertation, we carry out research to implement an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5V supply which has never been done before. We demonstrate that while its digitally controlled oscillator (DCO) can run directly at 0.5 V, an internal switched-capacitor dc–dc converter could be employed to ‘double’ the supply voltage to all the digital circuitry and particularly to regulate the TDC supply to stabilize its resolution, thus maintaining fixed in-band phase noise (PN) across process, voltage and temperature (PVT). The ADPLL supports 2-point modulation and forms a BLE transmitter realized in 28-nm CMOS. It maintains excellent in-band PN of -106 dBc/Hz (FoM of -239.2 dB) and RMS jitter of 0.86 ps while dissipating only 1.6mW at 40MHz reference. The power consumption reduces to 0.8mW during the BLE transmission when the DCO switches to open-loop. Furthermore, to go towards even lower voltages, we implement the first-ever deep sub-1V monolithic step-up dc–dc converter operating at 0.18–0.4V that outputs significant power for IoT with a peak power efficiency of 81.2% at 50 µW output power for the 0.18V input, and 87.1% at 300 µW output power for 0.4 V. It is implemented in 16-nm FinFET CMOS and uses a metal-oxide-semiconductor (MOS) transistor as a high-density flying capacitor for energy conversion. The capacitor is arranged in a self-biased deep N-well topology, which enhances the overall efficiency by 9.5%. An integrated time-to-digital converter (TDC) verifies the dc–dc output quality.