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  5. Design Methodology for Fractional-N Digital Frequency Synthesizers to Minimize System Jitter and Spurs
 
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Design Methodology for Fractional-N Digital Frequency Synthesizers to Minimize System Jitter and Spurs

Author(s)
Wang, Xu  
Uri
http://hdl.handle.net/10197/30575
Date Issued
2024
Date Available
2025-12-01T10:48:15Z
Embargo end date
2029-12-01
Abstract
Digital phase locked loops (DPLL’s) outperform charge-pump analog phase locked loops in design simplicity and power/area consumption, thanks to the full digitization of the time-to-digital converter (TDC) and digital loop filter; hence, they have become an attractive design option to serve as integrated frequency synthesizers for clocking, communication, radar, and instrumentation purposes. The adoption of coarse-resolution TDCs, e.g., 3-bit, 2-bit, and 1-bit (bangbang) TDCs, further reduces the hardware complexity and consumption for advanced DPLL synthesizers. However, their coarse quantization nonlinearity complicates the linearized analysis at both TDC-block and DPLL-system levels, which consequently makes it hard to perform accurate prediction and minimization of the system jitter and phase noise (PN). Furthermore, when using a digital Δ-Σ modulator to facilitate fractional-N frequency synthesis, the power of its quantization error (QE) can easily overwhelm the dynamic range of such TDCs and consequently cause nonlinear distortion that deteriorates the system PN/jitter. A priori cancellation of the QE by using a digital-to-time converter (DTC) before its injection into the loop is necessary in such fractional-N digital synthesizers. In DTC-enhanced fractional-N DPLLs, different genres of nonlinearities associated with the DTC have become the major nonlinearity concern of the whole system. Prior to the work described in this thesis, the detrimental PN and spurious responses caused by the DTC’s nonidealities, let alone their mitigation, were not fully investigated or explained in the literature. In this thesis, accurate analysis of the system jitter, PN, and spurs is performed. A jitter-minimization-oriented DPLL-design strategy and comprehensive DTC-enhancement techniques are provided. Together, these help to achieve the optimized digital synthesizer design with minimized system jitter and spurs. Behavioral simulations confirm the accuracy and effectiveness of the methods.
Type of Material
Doctoral Thesis
Qualification Name
Doctor of Philosophy (Ph.D.)
Publisher
University College Dublin. School of Electrical and Electronic Engineering
Copyright (Published Version)
2024 the Author
Subjects

PLL

Frequency synthesizer...

Fractional-N

Digital delta-sigma m...

Language
English
Status of Item
Peer reviewed
This item is made available under a Creative Commons License
https://creativecommons.org/licenses/by-nc-nd/3.0/ie/
File(s)
No Thumbnail Available
Name

XWang_PhD_Thesis_Final.pdf

Size

12.03 MB

Format

Adobe PDF

Checksum (MD5)

80e69d7827a4f4ea001fa12b404df334

Owning collection
Electrical and Electronic Engineering Theses

Item descriptive metadata is released under a CC-0 (public domain) license: https://creativecommons.org/public-domain/cc0/.
All other content is subject to copyright.

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