Digital Deep-Submicron CMOS Frequency Synthesis for RF Wireless Applications

Traditional designs of commercial frequency synthesizers for multi-GHz mobile RF wireless applications have almost exclusively employed the use of a charge-pump phase-locked loop (PLL), which acts as a local oscillator (LO) for both transmitter and receiver. Unfortunately, the circuits and techniques required are extremely analog intensive and utilize a process technology which is incompatible with a digital baseband. The author's research related to low-power and low-cost radio solutions has led to a novel all-digital synthesizer architecture that exploits strong advantages of a deep-submicron digital CMOS process technology as well as advances in digital very large scale of integration (VLSI) field. Its underlying theme is to maximize digitally-intensive implementation by operating in a synchronous phase domain. Chief benefit obtained with this architecture is to allow to integrate the RF front-end with the digital back-end onto a single silicon die. The presented frequency synthesizer naturally combines the transmitter modulation capability implemented in an all-digital manner. The pulse-shaping transmit filter and a class-E power amplifier are included to demonstrate the use of the proposed synthesizer in a targeted RF application. The ideas developed in this research project have been implemented in a Texas Instruments' deep-submicron CMOS process and demonstrated in a working silicon of Bluetooth transmitter for short-range communications.