Electrical and Electronic Engineering Theses

To satisfy the strict ultra-low-power (ULP) requirements of Internet-of-Things (IoT) applications, frequency generators, as one of the most power hungry IoT blocks, must achieve high power efficiency while maintaining low phase noise (PN). The PN of frequency synthesizers is mainly determined by 1) phase detector's (PD) noise affecting in-band, and 2) oscillator's PN affecting out-of-band spectra. Traditional analog charge-pump-based phase-locked loops (PLL) face the performance degradation of PD due to the short-channel effects and limited voltage headroom of transistors in advanced technology. They also suffer from the large area occupied by bulky analog loop filters. All-digital PLLs (ADPLL) are highly compatible with the technology scaling and offer a seamless digitally intensive calibration. However, the limited linearity and resolution of a time-to-digital converter (TDC) degrades the phase noise performance. Targeting the ULP requirements in advanced CMOS technology, an oscillator of high power efficiency, and a PD of ultra-low noise in the fractional-N operation are highly sought candidates to realize RF and mm-wave frequency synthesis of high performance. In this thesis, I first propose a compact ULP 2-2.8 GHz digitally controlled oscillator (DCO), which operates at an ultra-low 0.2-0.3 V supply voltage to support energy harvesting for IoT applications. A new inverse class-F23 operation is demonstrated, which intentionally reduces the harmonics in the waveform to reduce the 1/f noise up-conversion by a proposed high magnetic-coupling (km) transformer. The upconverted phase-noise flicker (1/f3) corner reaches below 100 kHz over a 35% tuning range. Secondly, I introduce a reference-sampling all-digital PLL (RS-ADPLL) avoiding the typical power-hungry low-noise reference buffer to achieve low power and large locking range. The necessarily low time-to-voltage gain during the reference sampling is compensated by a two-stage gated amplifier which also reduces the next stage quantization noise from an ADC. By means of this digitally intensive implementation, the detector offset can be calibrated out in digital blocks. The proposed ADPLL reaches -249 dB FoMjitter with 1.1 mW power consumption. Followed by this work, I demonstrate, for the first time ever, a reference oversampling (ROS) ADPLL supporting fractional-N operation. By using a bottom-plate sampling and common-mode (CM) voltage zero-forcing technique, the proposed PD achieves a 4x reference frequency detection rate to reduce the PD noise and re-locking time under the low-power condition. The fractional-N phase is compensated with capacitive DACs controlled by a sinusoidal look-up-table (LUT) and the same DACs also preset the CM voltage for oversampling to obtain high power efficiency. The proposed 2-2.3 GHz ADPLL achieves -247 dB FoMjitter while only consuming 1.15 mW. Finally, the proposed ROS PD technique is extended to millimeter-wave (mmW) application. A novel 24--31 GHz fractional-N mmW ADPLL is introduced employing the ROS-PD. With the 4x reference frequency operation of the loop, the proposed ROS-ADPLL achieves 237 fs while using a standard 50 MHz reference frequency. Together with the class-F3 oscillator and 3rd harmonic extraction, the whole system consumes 11.5 mW leading to FoMjitter-N of -269.3 dB.

This thesis focuses on the design, analysis, and implementation of a low phase noise (PN) rotary traveling-wave oscillator (RTWO) system that meets the stringent PN requirements of millimeter-wave (mmW) radar in the 76-81 GHz band. There are three main objectives of this work. The first is to explore techniques for reducing the flicker noise upconversion in an RTWO. The second is to find new techniques to enhance the DC-to-RF efficiency and to lower the power consumption of a frequency quadrupler by exploiting the multi-phase nature of an RTWO. Third, the feasibility of implementing an RTWO with an embedded phase-to-digital converter (PDC) at 10 GHz will be investigated. The thesis begins by discussing the stringent PN requirements in a frequency-modulated continuous-wave (FMCW) radar system in the 76-81 GHz band. Then, the PN requirements of an RTWO-based all-digital phase-locked loop (ADPLL), and considerably the RTWO, are derived for different frequency bands; 10, 20, and 26 GHz. Then, the novel "distributed stubs" technique is introduced to mitigate the flicker noise upconversion mechanism in mmW RTWOs. A comprehensive mathematical analysis is demonstrated to analyze the flicker noise upconversion mechanism and validate the effectiveness of the proposed technique. The proposed 26.2-30 GHz RTWO is implemented in 22 nm fully-depleted silicon-on-insulator (FD-SOI) CMOS for multi-phase clock generation featuring an ultra-low flicker PN corner. At 30 GHz, it achieves PN of -107.6 and -128.9 dBc/Hz at 1 MHz and 10 MHz offsets, respectively. This translates into figures-of-merit (FoMs) of 184.2 and 185.4 dB, for a single-phase, respectively. The proposed architecture consumes 20 mW from a 0.8 V supply. It achieves best-in-class performance with a flicker noise corner of 180 kHz, which is an order of magnitude better than currently reported among RTWOs. Next, a new technique is devised to implement a 32-42 GHz frequency quadrupler that performs digital logic operations between four phase-shifted differential signals at one-fourth of the output frequency. The four phase-shifted signals are generated by a 10 GHz RTWO and are symmetrically routed to the quadrupler using a CMOS buffered clock tree. The harmonic rejection ratio (HRR) is enhanced by employing a differential LC filter tuned at its output center frequency. The proposed frequency quadrupler is implemented in 22 nm FD-SOI CMOS. At 37 GHz, it produces an output power of -4 dBm with a 10% drain efficiency. It consumes 4 mW from a 0.8 V supply and occupies a core area of 0.021 mm2. The worst-case HRR for the fundamental, second, third, and fifth harmonics is 41.3, 48.6, 41.3, and 37.3 dBc, respectively. The DC-to-RF efficiency is better than what can be potentially achieved by other quadrupling techniques. Finally, a 10 GHz RTWO with 32 differential phases was demonstrated. It can act as a DCO and PDC simultaneously, thus simplifying the targeted ADPLL architecture while maintaining an excellent PN. The proposed 8.1-10.3 GHz RTWO is also implemented in 22 nm FD-SOI CMOS. It is digitally tuned using the non-uniform distributed frequency tuning technique to achieve an average frequency resolution of 750 kHz/LSB. The PDC with 32 embedded phases achieves a time resolution of 1.5-1.9 ps. The proposed architecture consumes 30.4 mW from a 0.8 V supply. At 9.3 GHz, it achieves PN of -113.3 and -133.9 dBc/Hz at 1 MHz and 10 MHz offsets, respectively. This corresponds to FoMs of 177.3 and 178 dB, for a single-phase, respectively.